1. Field of the Invention
The invention relates in general to the fabrication of semiconductor integrated circuits (ICs), and more particularly to a method of fabricating a border-less via.
2. Description of the Related Art
As methods of fabricating semiconductor devices become more and more advanced, the physical dimensions of the semiconductor devices become more and more critical. Thus, in an integrated circuit, the design rule that a via must be fabricated such that it has a border is crucial. To minimize the border of a via, and even to eliminate dimension limitations caused by the via border, are major tasks for meeting the requirements demanded of the fast-growing semiconductor fabrication industry.
Referring to FIG. 1 and FIG. 2, a conventional method of fabricating a via is shown. A conductive layer 12 is formed on a dielectric 10. By using photolithography and etching processes, the conductive layer 12 is patterned into metal lines. The gap 14 between the metal lines is filled with an insulating material. An insulating layer 16 is formed over the conductive layer 12. Again by using the photolithography and etching processes, a via 18 is patterned and then filled with metal, such as tungsten (W). Finally, another metal line is formed on top of the via 18 by which the upper conductive layer and the lower conductive layer are connected. To avoid misalignment which may be caused during the stepper or fabrication process, a border 17 normally exists around the via. That is, the conductive layer 12 must be formed such that the metal line is wide enough to prevent the via 18 being formed beyond the edge of the conductive layer 12. The existence of the via border helps to avoid the phenomenon of an open via or the etching through of the underlying layer. The "border design rule", or minimum overlap space between the conductive layer and the via, normally depends on the controllability of the stepper and the fabrication.